A known bipolar type semiconductor device, a bipolar transistor, is as disclosed in Japanese Patent Application Laid-open No. 4-330730.
FIG. 1 is a longitudinally-sectional view showing this conventional semiconductor device. In this semiconductor device, a high-concentration N.sup.+ -type collector buried region 2 which contains arsenic as an impurity is selectively formed on a P.sup.- -type single crystal silicon substrate 1 having a resistivity of 10 to 20 .OMEGA.cm, and an N.sup.- -type single crystal epitaxial layer 3 having an impurity concentration of 5.times.10.sup.15 cm.sup.-3 is formed at a thickness of 1.0 .mu.m over the whole surface of the buried region 2. The epitaxial layer 3 is separated into a plurality of island regions by oxide films 4 which are formed to extend to the substrate 1 by a well-known selective oxidation method. In FIG. 1, only one island region 3 corresponding to the buried region 2 is illustrated. The island type region 3 is further separated into two parts by an oxide film 4' extending to the buried region 2. One part of the island region 3 at the left side is designed to act as a collector region while the other part at the right side is designed to act as an N.sup.+ -type collector draw-out region 5 and thus it is subjected to a phosphor diffusion treatment in a subsequent process to be highly doped. Through this process, a silicon substrate or body 100 is formed.
The substrate 100 is covered with a silicon nitride film 7, through which an opening 101 for partially exposing the collector region 3 and for forming a base and an opening 102 for exposing the collector draw-out region 5 are formed. Preferably, a thin silicon oxide film is formed beneath the silicon nitride film 7.
A P.sup.+ -type polycrystalline silicon film 6 is selectively formed on the silicon nitride film 7, and it is designed to horizontally extend from the edge of the opening 101 toward the center of the opening 101, and a P-type polycrystalline silicon film 9 is further formed on the lower surface of the extended portion of the silicon film 6 toward the collector region 3. In addition, a P-type base region 8 of single crystal silicon is formed on the exposed portion of the collector region 3 by an epitaxial growth method, and the polycrystalline silicon film 9 and the base region 8 contact each other.
Further, an N.sup.+ -type polycrystalline silicon layer 11 is formed at the opening 102 in contact with the collector draw-out region 5. The base region 8 and the polycrystalline silicon films 6 and 9 are covered with silicon oxide films 13 and 14 except for an emitter forming portion. An N-type emitter region 10 of single crystal silicon is formed on the exposed portion of the base region 8, and an emitter electrode 12-1, a base electrode 12-2 and a collector electrode 12-3 of aluminum are formed in contact with the emitter region 10, the polycrystalline silicon film 6 and the polycrystalline silicon layer 11, respectively. This transistor is hereinafter referred to as the "first transistor".
In addition to the above publication, Japanese Patent Application No. 4-322432 discloses a technique for crystallizing polycrystalline silicon for a base electrode to obtain a single crystal silicon by a solid phase epitaxial growth method.
Such a crystallizing technique as described above will be described in detail with reference to FIG. 2.
In this technique, a buried collector layer 2, an epitaxial layer 3 and an oxide film 110 are successively formed in this order on a Si substrate 1, and an opening 120 is formed through the oxide film 110. Subsequently, an amorphous SiGe film is formed on the exposed epitaxial layer 3 and oxide film 110, and then it is replaced by a single crystal SiGe film 8 and a polycrystalline SiGe film 9 using the solid phase epitaxial growth method. Thereafter, an emitter film 10 is formed on the single crystal SiGe film 8. This transistor is hereinafter referred to as the "second transistor". In FIG. 2, reference numerals 111, 112 each denote a silicon oxide film, 200 an emitter electrode, 201 a base electrode, 202 a collector electrode, 11 a collector film, 57 a collector wall layer, 54 a trench for element isolation, 55 a P.sup.+ -type layer for channel cut, and 56 a silicon oxide film.
Through this process, the base-collector junction capacitance can be reduced, and the base layer and the base electrode draw-out layer can be formed in self-alignment.
However, the semiconductor devices as described above have the following problems.
With respect to the first transistor, when SiGe is grown as an intrinsic base by a selective epitaxial growth method, the growth rate of polycrystalline SiGe is lower than that of single crystal SiGe (epitaxial SiGe). The difference in growth rate is dependent on the concentration of Ge. For example, for Ge=10%, i.e. for Si.sub.0.9 Ge.sub.0.1, the ratio of the polycrystalline SiGe growth rate to the epitaxial SiGe growth rate (poly/epi growth rate ratio) is equal to 1/5 to 1/4. Therefore, when the thickness of the base region 8 is made thin enough to maintain the necessary characteristics of the transistor, the thickness of the silicon nitride film 7 should be made thinner. As a result, the distance between the polycrystalline silicon film 6 and the collector region 3 is shortened, so that the parasitic capacitance between the base and the collector is increased.
With respect to the second transistor, the polycrystalline SeGe deposited in the same process is subjected to the solid phase epitaxial growth treatment to form the intrinsic base 8 and the base film 9. Accordingly, the thickness of the base film is substantially equal to that of the intrinsic base. In order to improve a cut-off frequency f.sub.T, the thickness of the intrinsic base must be reduced. However, in this case the thickness of the base film is also reduced, resulting in increase of a base resistance R.sub.b. That is, a trade-off is imposed between f.sub.T and R.sub.b, so that the transistor cannot be improved in performance as a whole.